Computer Engineering @ Boston University

Ozan
Ekame

Hardware-to-software engineer — Verilog logic gates up to C++ compiled to WASM running natively in the browser. Five languages, one obsession: understanding how things actually work.

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About Me

Three Continents, One Stack

As a kid I'd lose hours to Legos, wiring projects, anything I could take apart and put back together differently. What I was really chasing was that moment when something you built actually comes to life, my own little Frankenstein. That instinct never left.

I'm Ozan, born in Istanbul, raised in Barcelona, now at Boston University studying Computer Engineering. I chose CE specifically because it scared me a little, and that's always been my signal to go. It's also the one field where you can trace a complete path from electrons to a web app, and then hand that web app to someone on the other side of the world. Speaking five languages gave me a specific ambition: I don't just want to build things, I want to spread them. The engineers who actually change the world are the ones who can communicate across every boundary.

My strongest skill is probably obsessive curiosity. The Color Sorter won a class award not because of fancy parts, but because I ran hundreds of calibration trials, obsessed over why the sensor drifted in different lighting, and engineered the thresholds until it hit 95% consistently.

Outside the lab I lead. As a BU Engineering Student Advisor I mentor incoming freshmen, and as a youth basketball coach I run drills, manage game-day decisions, and teach kids to compete as a unit. I'm also active in the AI Society, Mars Rover Club, and Barbell Club. Piano, surfing, and an embarrassing record collection keep me human.

Languages Spoken

🇪🇸 Spanishnative 🇹🇷 Turkishnative 🇬🇧 Englishnative 🏳 Catalanfluent 🇫🇷 Frenchintermediate

Projects

Comp. Engineering

Languages spoken

May
'27

Graduation

Experience

Work & Involvement

BU College of Engineering Student Advisor Volunteer

Summer 2025 – Present

Boston University

Boston, MA

Advising incoming students on academic paths, course planning, and engineering program resources.

Sales & Product Management Intern

May 2024 – Aug 2024

Dima Textile

Barcelona, Spain

Expanded customer base by presenting product lines directly to prospective clients at company HQ.
Tracked garment production in Excel to ensure accurate, on-time delivery.

IT Support Technician Intern

Jul 2022

Alliance Healthcare

Istanbul, Turkey

Troubleshot hardware and software issues; assisted with server security maintenance and order-tracking systems.

Education

Academic Background

Boston University, College of Engineering

B.S. Computer Engineering

Physics-first approach applied to circuits, digital logic, and embedded systems. Student Advisor for the College of Engineering. Member of AI Society, Mars Rover Club, and Barbell Club.

Computer ArchitectureVLSI Design CircuitsLogic & Design ElectronicsSoftware Engineering AlgorithmsDiscrete Math Probability & Statistics

Expected
May 2027

Color Sorter Machine CLASS WINNER

EK210 · Arduino + TCS34725 · Jan–May 2025

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The Problem

Our EK210 team design challenge was to build a fully automated machine that could physically sort objects by color with minimal human intervention. As a team, we had to coordinate mechanical design, electronics, and software under a tight semester timeline. Manual sorting is slow and error-prone — we needed a reliable, reproducible system using affordable parts.

The Solution

I owned the full sensing and software pipeline: an Adafruit TCS34725 RGB sensor reads R/G/B/C values over I²C, an Arduino classifies the color using tunable threshold windows, a servo positions the drop chute, and a NEMA17 stepper advances the bin disk. I coordinated with teammates on mechanical integration — aligning sensor placement with the chute geometry and timing the stepper with the servo. A 20×4 I²C LCD displays live per-color counts.

Arduino C++I²CServo PWMStepper ControlTCS34725TB6600 DriverLCD Display

What I Learned

Calibrating optical sensors in variable ambient light taught me that hardware accuracy is a loop, not a one-time setting. I learned how to write modular firmware (one sketch per concern), manage shared grounds across mixed-voltage rails (3.3 V sensor, 5 V logic, 12 V stepper), and translate a physical concept into a deterministic control loop. The machine won the class award for highest accuracy and lowest cost.

My role: Code & sensor/LCD wiring — wrote all Arduino firmware and tuned detection thresholds across 100 test trials.

FPGA Binary Conversion Game

Verilog · Xilinx Nexys A7 · 100 MHz · Jan–May 2025

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FPGA Binary Conversion Game — Nexys A7 board

The Problem

Design and implement a complete digital logic system on a real FPGA using only Verilog — no processors, no firmware, no shortcuts. The goal was to build something interactive that exercises every layer of hardware design: timing, state control, I/O, and display multiplexing, all running at 100 MHz.

The Solution

I built a binary conversion game on the Xilinx Nexys A7. A pseudo-random counter generates a decimal number shown on the 7-segment display. The player uses 12 switches to enter its binary equivalent and presses OK to submit. Correct answers light an LED and expand the difficulty range. The full stack is pure Verilog: a top-level FSM, a Binary-to-BCD converter using integer division, a multiplexed 7-segment driver refreshing at ~1 kHz, hardware debounce logic, and a clock divider. Each module has its own testbench simulated in Vivado.

Verilog HDLFSM DesignVivadoXilinx Nexys A7Binary→BCD7-Seg MuxClock DividerTestbenches

What I Learned

This project made clock domains, propagation delays, and synthesis constraints concrete — not just textbook concepts. Writing testbenches forced me to think adversarially about edge cases before touching hardware. I learned how to decompose a complex system into independently verifiable modules, and why a well-structured FSM makes the rest of the design simple. It was my first end-to-end experience taking HDL from simulation to a running bitstream on real silicon.

Unit Converter Web App

EC327 · C/C++ → WASM · JavaScript · Sep–Dec 2024

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The Problem

Build a unit converter web app for EC327 (Software Engineering) that works fully offline, supports 15+ conversion categories, handles custom unit rules, and runs all calculations with native precision — not just JavaScript's floating-point approximations.

The Solution

The back end is written in C/C++ and compiled to WebAssembly, so every calculation runs natively inside the browser at near-native speed. The JavaScript front end handles UI events, routes inputs to the WASM module, and manages a history log that users can download as a .txt file. Custom unit rules let users define conversion formulas using +/−/×/÷ with a variable x. We worked around a CORS issue (that blocked a local-server approach) by embedding everything into a single HTML file.

WebAssemblyC / C++JavaScriptHTMLOffline-FirstCustom Unit EngineHistory Export

What I Learned

This was my first real exposure to the WASM compilation pipeline — taking C++ unit field logic, compiling it with Emscripten, and bridging it into a live web page. I learned how browser security policies (CORS) shape architecture decisions, how to work effectively in a 7-person team across front-end and back-end boundaries, and how to write reusable C++ conversion modules that are testable independently of the UI.

My role: Back-end unit fields (C/C++), WASM compilation pipeline, integration testing. ~50% of back-end work.

YAGS Branch Predictor

EC513 · C++ in gem5 · Jan–May 2026

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The Problem

Branch prediction is critical for modern out-of-order processors. The central problem with global predictors is PHT aliasing: two different branches mapping to the same Pattern History Table entry. When aliasing is destructive, mispredictions follow and the pipeline stalls.

The Solution

We implemented the YAGS (Yet Another Global Scheme) predictor as a new BPredUnit subclass in gem5. YAGS splits prediction into a Choice PHT that captures each branch's dominant bias, and two tagged direction caches that store only the exceptions to that bias. 13-bit tags from the branch PC virtually eliminate aliasing between consecutive branches. We evaluated on five SPEC CPU 2017 benchmarks (mcf, omnetpp, xalancbmk, gcc, x264) against five existing gem5 predictors.

C++gem5 SimulatorBranch PredictionSPEC CPU 2017O3CPU ModelBU SCC Cluster

What I Learned

Working inside gem5's codebase taught me how real microarchitectural simulators are structured and how to add hardware models that plug into an existing pipeline. I learned how saturating counters, tag matching, and cache indexing interact at the microarchitectural level. Debugging a segfault caused by address overflow during cache indexing reinforced the importance of bounds checking in low-level simulation code. Running long simulations on a shared HPC cluster (BU's SCC) introduced me to job scheduling and resource management in practice.

Team: Brian Quijada, Fadi Kidess, Ozan Ekame Pekgoz, Will Borland · Instructor: Prof. Ajay Joshi

APD Sense Amplifier for SRAM

EC571 · Cadence Virtuoso · 50 nm CMOS · Jan–May 2026

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The Problem

SRAM sense amplifiers face a fundamental tradeoff. Latch-type SAs are fast and power-efficient but fail when bitline swing is smaller than the input offset voltage, a problem that worsens at advanced nodes due to transistor mismatch. Current-mirror SAs are robust but draw continuous bias current the entire time sense-enable is asserted, wasting power after the output has already settled.

The Solution

We designed an Automatic Power-Down (APD) sense amplifier: a current-mirror SA paired with a monitoring circuit that detects when the output has settled and immediately cuts the bias current. The APD block uses Schmitt-trigger buffers with programmable thresholds, a high-skew NAND gate, and a dynamic inverter to generate the power-down signal. We also implemented a dual-threshold (dual-V_HL) extension that provides two selectable Schmitt trigger thresholds to handle process variation across corners. All design and simulation was done in Cadence Virtuoso at the 50 nm node.

Cadence VirtuosoVLSI Design50nm CMOSSRAMSense AmplifierSchmitt TriggerProcess Corners

What I Learned

This project gave me hands-on experience with transistor-level VLSI design in an industry-standard tool. I learned how to size transistors for specific voltage thresholds using analytical equations (Filanovsky & Bakes), how to design for process variation by providing configurable operating points, and how power-down techniques can dramatically reduce dynamic power without impacting the critical path. Simulating across process corners reinforced why robust design matters at advanced nodes.

Team: Ozan Ekame Pekgoz, William Borland · Instructor: Prof. Rabia Yazicigil Kirby

Ozan
Ekame

Three Continents, One Stack

What I've Built

Technical Proficiencies

Work & Involvement

Academic Background

Boston University, College of Engineering

Let's Connect

OzanEkame

Three Continents, One Stack

What I've Built

Technical Proficiencies

Work & Involvement

Academic Background

Boston University, College of Engineering

Let's Connect

Ozan
Ekame